The present invention relates to a semiconductor memory, and in particular to a one-transistor dynamic MOS memory which enables an increase in memory capacity without increasing the space required, and which is suitable for increasing memory size.
Each memory cell of a DRAM consists of a storage capacitor and a switching MISFET. The storage capacitor is constructed of a capacitor of the MIS type. Concretely, it is constructed of a semiconductor substrate, an insulator film which is formed on the semiconductor substrate, and a capacitor electrode which is formed on the insulator film and to which a predetermined voltage is applied. Charges in a quantity corresponding to the information of "1" or "0" are stored in an inversion layer which is formed within the semiconductor substrate under the capacitor electrode having the predetermined voltage applied thereto.
The memory size of MOS dynamic memories quadrupled in the approximately three years after a 1 K-bit dynamic random access memory (hereinafter referred to as a DRAM) was first developed early in the 1970's. 16-pin DIPs (dual-in-line packages) are namely used for accommodating memory chips, but this imposed a limitation on the size of the cavity for inserting the chips. Therefore, the size of the memory chip has increased by approximately 1.4 times, despite the fact that the degree of integration has quadrupled. (Since large quantities of DRAMs are used, it is necessary to curb any increase in the size of chips, if only from the standpoint of cost.) Therefore, the area of memory cell per bit of one storage unit is greatly reduced, i.e., is reduced to about one-third, owing to the quadrupled degree of integration. The capacity C of a semiconductor memory is expressed by C=.epsilon.A/T.sub.i (where .epsilon. is the permeability of the insulator, A the capacitor area, and T.sub.i the insulator thickness). Therefore, if the area A is reduced to one-third, the capacity C decreases to one-third so long as .epsilon. and T.sub.i remain the same. The signal quantity S of a memory capacitor changes in proportion with the charge quantity Qs stored, and the charge quantity Qs is a product of the capacity C and a memory voltage Vs. Therefore, the charge quantity Qs decreases with a decrease in the capacitor area A, and the signal quantity S decreases correspondingly.
If noise voltage is denoted by N, the signal-to-noise ratio (S/N ratio) decreases with a decrease in the signal quantity S, raising a problem with regard to the operation of the circuit. Usually, therefore, a decrease in the capacitor area A is compensated for by decreasing the insulator thickness T.sub.i. Therefore, as the degree of integration of DRAMs increases from 4 K bits, to 16 K bits, to 64 K bits, the typical thickness T.sub.i of the SiO.sub.2 film used as the insulator gradually decreases from 100 nm, to 75 nm and then to 50 nm, respectively.
Recently it has been confirmed that the amount of noise generated in a silicon substrate by alpha-particles radiated from radioactive heavy metals (such as U, Th, etc.) within the package becomes unacceptable if the electric charge is less than 200 fC (femtocoulombs). In order to maintain reliability in operation, therefore, it is not possible to reduce the signal quantity, i.e., the electric charge, below about 200 fC.
Because of these reasons, therefore, attempts have been made to reduce the thickness of the insulator further, raising a problem with regard to the dielectric breakdown of the insulator. The SiO.sub.2 film which is usually used as the insulator of the capacitor has a dielectric withstand electric field of a maximum of 10.sup.7 V/cm. Therefore, a 10 nm thick SiO.sub.2 film will break down permanently, or be degraded, when a voltage of 10 volts is applied. Using such a device close to its maximum dielectric withstand electric field invites a serious problem with regard to its long-term reliability, even if it does not break down permanently in short-term usage.
FIG. 1 is a diagram of the construction of a one-transistor DRAM memory cell which consists of a capacitor 1 for storing electric charge, and a switching MOS transistor 2. The drain of the switching MOS transistor is connected to a bit line 3, and its gate is connected to a word line 4.
This memory cell is operated by reading out the signal charge stored in the capacitor 1 by the switching MOS transistor 2. In practice, the construction of a large-scale integrated memory is formed of a memory area by methods which can be roughly divided into the two described below.
FIG. 2 shows the so-called "open-bit line" construction in which bit lines 3-1 and 3-2 are arrayed on either side of a sense amplifier 5 which amplifies signals in a differential manner. In this construction, only one bit line, 3-1, electrically crosses one word line 4-1, and the difference in signals between the bit line 3-1 and the bit line 3-2 is detected by the sense amplifier 5.
FIG. 3 illustrates the so-called "folded-bit line" construction in which two bit lines 3-1 and 3-2 connected to the sense amplifier 5 are arrayed in parallel, so that one word line 4-1 intersects both bit lines 3-1 and 3-2.
Various embodiments of the present invention described below pertain chiefly to the folded-bit line construction. The invention described regarding these embodiments, however, can also be adapted to the open-bit line construction.
As shown in FIGS. 2 and 3, if the stray capacitance of a stray capacitor 6 of the bit line 3-2 is denoted by C.sub.D and the capacity of capacitor 1-2 of the memory cell by C.sub.S, one of the main figures of merit of the memory array is expressed by C.sub.S /C.sub.D. The S/N ratio of the memory array corresponds exactly to C.sub.S /C.sub.D. To improve the S/N ratio, furthermore, it is important to increase the capacity of the capacitor of the memory cell, and reduce the stray capacitance C.sub.D of the bit line 3.
FIG. 4 is a plan view of the construction of a memory cell of the folded-bit line type, and FIG. 5 is a section thereof taken along the line A-A' of FIG. 4. As can be seen from FIGS. 4 and 5, a capacitor is formed in a portion of an active region which is surrounded by a field oxidation film 11 of a thickness of usually more than 100 nm. The active region 7 is covered by a plate 8, but the plate 8 is selectively removed from the portion where a switching transistor will be formed and from the portion of contact hole 9 through which the bit line 3 will be connected to a drain 15 on the silicon substrate (region 80 in FIG. 4). Word lines 4-1 and 4-2 are attached in this portion to form the gates of the switching transistors 2, as shown in FIG. 5.
One method of forming a semiconductor memory of this type is described below. For ease of comprehension, the transistor described here is of the n-channel type. To form a p-channel transistor, the conductivity types of the silicon substrate and of the diffusion layer should be opposite to those of the n-channel transistor.
FIG. 5 is a section taken along the line A-A' of FIG. 4.
In the conventional memory cell shown in FIG. 5, a field SiO.sub.2 film 11 is formed selectively to a thickness of usually 100 to 1000 nm on a p-type silicon substrate 10 having a resistivity of about 10 ohm -cm, by the so-called LOCOS method using a thermal oxidation mask composed of Si.sub.3 N.sub.4. The plate 8 is deposited selectively thereon, the plate 8 being composed of polycrystalline silicon doped with phosphorus or arsenic ions. The surface of the polycrystalline silicon plate 8 is then oxidized to form a first intermediate oxide film 13. The word line 4-1 is deposited, the word line 4-1 being composed of polycrystalline silicon, molybdenum silicide, or a refractory metal (molybdenum or tungsten), followed by the implantation of phosphorus or arsenic ions. Thus, N.sup.+ -type diffusion layers 15 are formed in the active regions where no plate 8 or word line 4-1 is deposited, to form the source and drain of the switching MOS transistor 2. Thereafter, PSG (phospho-silicate glass) containing phosphorus is deposited to a thickness of 200 to 1000 nm by the so-called CVD method to form a second intermediate insulator 14, a contact hole 9 is formed in the place where the bit line 3-2 indicated by an aluminum electrode is to be connected to the diffusion layer 15, and the bit line 3-2 is selectively deposited.
In the thus-formed memory cell, the area occupied by the region 16 of the capacitor 1 acting as the memory capacitor inevitably decreases with a decrease in the size of the memory cell. Unless the thickness of the gate oxide film 12 is reduced, therefore, the capacity C.sub.S decreases to raise a serious problem concerning memory operation.
In the above description, the same SiO.sub.2 insulation film 12 lies beneath the plate 8 and the word line 4-1 (i.e., the gate of the switching MOS transistor 2). When it is desired to increase the capacity C.sub.S of the memory cell, however, the insulation film beneath the plate 8 can be formed to have a one- to three-layer construction using either SiO.sub.2 or Si.sub.3 N.sub.4, or both.
The solve the above problems, a memory has been proposed by one of the inventors of the present application, in which a narrow groove is formed in the silicon substrate, and a capacitor that acts as the memory capacitor is formed on the surfaces of the groove (Japanese Patent Application No. 50-53883 filed May 7, 1975 and laid open as Japanese Kokai No. 51-130178 on Nov. 12, 1976).
In this previously proposed memory, the side and bottom surfaces of the groove are utilized as the electrode surfaces of the capacitor, providing the advantage that the electrode area is considerably increased without increasing the space required, compared with the memory of the construction shown in FIGS. 4 and 5. More specifically, this storage capacitor element is of MIS (i.e., metal insulator semiconductor) type and is composed of moats (which are also called "U-shaped grooves") formed to extend inward from one main surface of the semiconductor substrate, an insulating film formed to extend along those moats, and a capacitor electrode formed to cover said insulating film. On the other hand, the switching transistor is constructed of an insulated gate type field effect transistor (which will be abbreviated as "MISFET"), which is specifically composed of a source region and a drain region formed in the semiconductor substrate at a spacing from each other, and a gate electrode formed through the insulating film over the semiconductor substrate between said source region and said drain region. However, it should be noted that in this arrangement, the charges are stored in a depletion layer and an inversion layer within the semiconductor substrate, and this can cause problems with regard to high-density integration. Specifically, the memory cell of this type cannot exclude the influence of minority carriers appearing due to alpha-particles or minority carriers injected from a peripheral circuit portion, etc. Insofar as the charges are stored in the depletion layer and the inversion layer, the quantity of charges fluctuates due to the minority carriers. Accordingly, the occupying area of a storage capacitor cannot be made smaller than a certain value. Since the influence of the minority carriers increases more in a place deeper from the surface of a semiconductor substrate, deepening a trench is not very effective. The unnecessary minority carriers drop the voltage, which is held in the depletion layer of the storage capacitor, to invert the "0" information to the "1" information thereby to cause the erroneous operations (or the software errors) of the information reading operations. In order to obtain a predetermined charge storage for coping with the unnecessary minority carriers caused by the alpha-rays, moreover, the depth of the pores is limited so that the integration of the DRAM cannot be significantly improved.
Moreover, with the memory cells of the specified type, it is impossible to make small an isolation region for electrically isolating the adjacent memory cells. The reason is that, since the depletion layers and inversion layers of the capacitors of the adjacent memory cells need to be prevented from coupling, the distance between the memory cells cannot be made smaller than a certain value. In case of employing a field oxide film as the isolation region, the problem of bird's beak is also involved. Meanwhile, the depletion layer couples to the depletion layer of the adjacent trench more easily in the deep part of the trench than in the shallow part thereof. For this reason, the distance between the trenches cannot be made smaller than a certain value.
Some of the inventors of the present invention have also proposed another memory (U.S. application Ser. No. 465,341). This earlier U.S. application discloses a semiconductor memory which is provided with a capacitor formed by utilizing a groove formed in the semiconductor substrate, and an insulated-gate field-effect transistor, and which prevents the depletion layer extending from the groove, as well as a process of manufacturing the memory. In that device, a layer 24 is diffused into the substrate walls of the groove to be used as a capacitor electrode for contacting the source or drain of the FET (see FIG. 24). Another electrode 8 formed in the groove is coupled to ground. The device and method proposed in this related U. S. patent application make it possible to increase the degree of integration of a semiconductor integrated circuit. To further increase the degree of integration of a semiconductor integrated circuit, however, it is necessary to provide a semiconductor device which is capable of producing a desired storage capacity even if the space required by the memory cell is further decreased. Also, it is desired to limit noise to a greater extent than is done in this earlier U. S. application since such noise becomes more of a problem as the device size is decreased.